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january 17, 2006 ? cypress semiconductor corp. 2005-2006 ? document no. 001-05356 rev. *a 1 psoc? mixed-signal array preliminary data sheet cy8c20334 and cy8c20434 psoc? functional overview the psoc family consists of many mixed-signal array with on- chip controller devices. these devices are designed to replace multiple traditional mcu-based system components with one, low cost single-chip programmable component. a psoc device includes configurable analog and digital blocks, as well as pro- grammable interconnect. this architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. additionally, a fast cpu, flash program memory, sram data memory, and config- urable io are included in a range of convenient pinouts. the psoc architecture for this device family, as illustrated on the left, is comprised of three main areas: the core, the system resources, and the capsense analog system. a common, ver- satile bus allows connection between io and the analog sys- tem. each cy8c20x34 psoc device includes a dedicated capsense block that provides sensing and scanning control cir- cuitry for capacitive sensing applications. depending on the psoc package, up to 28 general purpose io (gpio) are also included. the gpio provide access to the mcu and analog mux. features low power capsense block ? configurable capacitive sensing elements ? supports combination of capsense buttons, sliders, touchpads and proximity sensors powerful harvard architecture processor ? m8c processor speeds running up to 12 mhz ? low power at high speed ? 2.4v to 5.25v operating voltage ? commercial temperature range: -20c to +70c flexible on-chip memory ? 8k flash program storage 50,000 erase/write cycles ? 512 bytes sram data storage ? partial flash updates ? flexible protection modes ? interrupt controller ? in-system serial programming (issp ? ) complete development tools ? free development tool (psoc designer?) ? full-featured, in-circuit emulator and programmer ? full speed emulation ? complex breakpoint structure ? 128k trace memory precision, programmable clocking ? internal 5.0% 6/12 mhz main oscillator ? internal low speed oscillator at 32 khz for watchdog and sleep programmable pin configurations ? pull up, high z, open drain, cmos drive modes on all gpio ? 5 ma strong drive mode on port 1 ? up to 28 analog inputs on gpio ? configurable inputs on all gpio ? selectable, regulated digital io on port 1 - - 3.0v, 20 ma total source current versatile analog mux ? common internal analog bus ? simultaneous connection of io combinations ? comparator noise immunity ? low-dropout voltage regulator for the analog array additional system resources ? configurable communication speeds -- i2c: selectable to 50 khz, 100 khz or 400 khz -- spi : configurable between 46.9 khz and 3 mhz ? i 2 c? slave ? spi master and spi slave ? watchdog and sleep timers ? internal voltage reference ? integrated supervisory circuit
january 17, 2006 document no. 001-05356 rev. *a 2 cy8c20x34 preliminary data sheet psoc? overview the psoc core the psoc core is a powerful engine that supports a rich instruction set. it encompasses sram for data storage, an interrupt controller, sleep and watchdog timers, and imo (inter- nal main oscillator) and ilo (internal low speed oscillator). the cpu core, called the m8c, is a powerful processor with speeds up to 12 mhz. the m8c is a two-mips, 8-bit harvard architec- ture microprocessor. system resources provide additional capability, such as a con- figurable i2c slave/spi master-slave communication interface and various system resets supported by the m8c. the analog system is composed of the capsense psoc block and an internal 1.8v analog reference, which together support capacitive sensing of up to 28 inputs. the capsense analog system the analog system contains the capacitive sensing hardware. several hardware algorithms are supported. this hardware per- forms capacitive sensing and scanning without requiring exter- nal components. capacitive sensing is configurable on each gpio pin. scanning of enabled capsense pins can be com- pleted quickly and easily across multiple ports. analog system block diagram the analog multiplexer system the analog mux bus can connect to every gpio pin. pins can be connected to the bus individually or in any combination. the bus also connects to the analog system for analysis with the capsense block comparator. switch control logic enables selected pins to precharge continu- ously under hardware control. this enables capacitive mea- surement for applications such as touch sensing. other multiplexer applications include: complex capacitive sensing interfaces, such as sliders and touchpads. chip-wide mux that allows analog input from any io pin. crosspoint connection between any io pin combinations. additional system resources system resources, some of which have been previously listed, provide additional capability useful to complete systems. addi- tional resources include low voltage detection and power on reset. brief statements describing the merits of each system resource are presented below. the i2c slave/spi master-slave module provides 50/100/400 khz communication over two wires. spi communication over 3 or 4 wires runs at speeds of 46.9 khz to 3 mhz (lower for a slower system clock). low voltage detection (lvd) interrupts can signal the appli- cation of falling voltage levels, while the advanced por (power on reset) circuit eliminates the need for a system supervisor. an internal 1.8v reference provides an absolute reference for capacitive sensing. the 5v maximum input, 3v fixed output, low-dropout regula- tor (ldo) provides regulation for ios. a register-controlled bypass mode allows the user to disable the ldo. id ac reference buffer v r cintern al analog global bus cap sense counters comparator mu x mu x refs capsense clock select relaxation oscillator (ro) csclk imo
january 17, 2006 document no. 001-05356 rev. *a 3 cy8c20x34 preliminary data sheet psoc? overview getting started the quickest path to understanding the psoc silicon is by read- ing this data sheet and using the psoc designer integrated development environment (ide). this data sheet is an over- view of the psoc integrated circuit and presents specific pin, register, and electrical specifications. for in-depth information, along with detailed programming information, reference the psoc mixed-signal array technical reference manual , which can be found on http://www.cypress.com/psoc. for up-to-date ordering, packaging, and electrical specification information, reference the latest psoc device data sheets on the web at http://www.cypress.com. development kits development kits are available from the following distributors: digi-key, avnet, arrow, and future. the cypress online store contains development kits, c compilers, and all accessories for psoc development. go to the cypress online store web site at http://www.cypress.com, click the online store shopping cart icon at the bottom of the web page, and click psoc (program- mable system-on-chip) to view a current list of available items. technical training free psoc technical training is available for beginners and is taught by a marketing or application engineer over the phone. psoc training classes cover designing, debugging, advanced analog, as well as application-specific classes covering topics such as psoc and the lin bus. go to http://www.cypress.com, click on design support located on the left side of the web page, and select technical training for more details. consultants certified psoc consultants offer everything from technical assistance to completed psoc designs. to contact or become a psoc consultant go to http://www.cypress.com, click on design support located on the left side of the web page, and select cypros consultants. technical support psoc application engineers take pride in fast and accurate response. they can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm . application notes a long list of application notes will assist you in every aspect of your design effort. to view the psoc application notes, go to the http://www.cypress.com web site and select application notes under the design resources list located in the center of the web page. application notes are sorted by date by default. development tools psoc designer is a microsoft ? windows-based, integrated development environment for the programmable system-on- chip (psoc) devices. the psoc designer ide and application runs on windows nt 4.0, windows 2000, windows millennium (me), or windows xp. (reference the psoc designer func- tional flow diagram below.) psoc designer helps the customer to select an operating con- figuration for the psoc, write application code that uses the psoc, and debug the application. this system provides design database management by project, an integrated debugger with in-circuit emulator, in-system programming support, and the cyasm macro assembler for the cpus. psoc designer also supports a high-level c language compiler developed specifically for the devices in the family. psoc designer subsystems commands results psoc tm designer core engine psoc configuration sheet manufacturing inform ation file device database importable design database device programmer graphical designer in te r fa ce context sensitive help emulation pod in-c irc uit emulator project database application database user modules library psoc tm designer
january 17, 2006 document no. 001-05356 rev. *a 4 cy8c20x34 preliminary data sheet psoc? overview psoc designer software subsystems device editor the device editor subsystem allows the user to select different onboard analog and digital components called user modules using the psoc blocks. examples of user modules are adcs, dacs, amplifiers, and filters. the device editor also supports easy development of multiple configurations and dynamic reconfiguration. dynamic reconfig- uration allows for changing configurations at run time. psoc designer sets up power-on initialization tables for selected psoc block configurations and creates source code for an application framework. the framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of psoc block configurations at run time. psoc designer can print out a configuration sheet for a given project configuration for use during application pro- gramming in conjunction with the device data sheet. once the framework is generated, the user can add application-specific code to flesh out the framework. it?s also possible to change the selected components and regenerate the framework. application editor in the application editor you can edit your c language and assembly language source code. you can also assemble, com- pile, link, and build. assembler. the macro assembler allows the assembly code to be merged seamlessly with c code. the link libraries auto- matically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. c language compiler. a c language compiler is available that supports the psoc family of devices. even if you have never worked in the c language before, the product quickly allows you to create complete c programs for the psoc family devices. the embedded, optimizing c compiler provides all the features of c tailored to the psoc architecture. it comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. debugger the psoc designer debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the psoc device. debugger commands allow the designer to read the program and read and write data memory, read and write io registers, read and write cpu registers, set and clear break- points, and provide program run, halt, and step control. the debugger also allows the designer to create a trace buffer of registers and memory locations of interest. online help system the online help system displays online, context-sensitive help for the user. designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. this system also provides tutorials and links to faqs and an online support forum to aid the designer in getting started. hardware tools in-circuit emulator a low cost, high functionality ice (in-circuit emulator) is avail- able for development support. this hardware has the capability to program single devices. the emulator consists of a base unit that connects to the pc by way of a usb port. the base unit is universal and will operate with all psoc devices. emulation pods for each device family are available separately. the emulation pod takes the place of the psoc device in the target board and performs full speed (24 mhz) operation.
january 17, 2006 document no. 001-05356 rev. *a 5 cy8c20x34 preliminary data sheet psoc? overview designing with user modules the development process for the psoc device differs from that of a traditional fixed function microprocessor. the configurable analog and digital hardware blocks give the psoc architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. these configurable resources, called psoc blocks, have the ability to implement a wide variety of user-selectable functions. each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the io pins. iterative development cycles permit you to adapt the hard- ware as well as the software. this substantially lowers the risk of having to select a different part to meet the final design requirements. to speed the development process, the psoc designer inte- grated development environment (ide) provides a library of pre-built, pre-tested hardware peripheral functions, called ?user modules.? user modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. each user module establishes the basic register settings that implement the selected function. it also provides parameters that allow you to tailor its precise configuration to your particular application. for example, a pulse width modulator user mod- ule configures one or more digital psoc blocks, one for each 8 bits of resolution. the user module parameters permit you to establish the pulse width and duty cycle. user modules also provide tested software to cut your development time. the user module application programming interface (api) provides high- level functions to control and respond to hardware events at run time. the api also provides optional interrupt service routines that you can adapt as needed. the api functions are documented in user module data sheets that are viewed directly in the psoc designer ide. these data sheets explain the internal operation of the user module and provide performance specifications. each data sheet describes the use of each user module parameter and documents the set- ting of each register controlled by the user module. the development process starts when you open a new project and bring up the device editor, a graphical user interface (gui) for configuring the hardware. you pick the user modules you need for your project and map them onto the psoc blocks with point-and-click simplicity. next, you build signal chains by inter- connecting user modules to each other and the io pins. at this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. when you are ready to test the hardware configuration or move on to developing code for the project, you perform the ?generate application? step. this causes psoc designer to generate source code that automatically configures the device to your specification and provides the high-level user module api functions. user module and source code development flows the next step is to write your main program, and any sub-rou- tines using psoc designer?s application editor subsystem. the application editor includes a project manager that allows you to open the project source code files (including all gener- ated code files) from a hierarchal view. the source code editor provides syntax coloring and advanced edit features for both c and assembly language. file search capabilities include simple string searches and recursive ?grep-style? patterns. a single mouse click invokes the build manager. it employs a profes- sional-strength ?makefile? system to automatically analyze all file dependencies and run the compiler and assembler as nec- essary. project-level options control optimization strategies used by the compiler and linker. syntax errors are displayed in a console window. double clicking the error message takes you directly to the offending line of source code. when all is correct, the linker builds a hex file image suitable for programming. the last step in the development process takes place inside the psoc designer?s debugger subsystem. the debugger down- loads the hex image to the in-circuit emulator (ice) where it runs at full speed. debugger capabilities rival those of systems costing many times more. in addition to traditional single-step, run-to-breakpoint and watch-variable features, the debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. debugger interface to ice application editor device editor project manager source code editor storage inspector us e r module selection placement and parameter -ization generate application build all event & breakpoint manager build manager source code generator
january 17, 2006 document no. 001-05356 rev. *a 6 cy8c20x34 preliminary data sheet psoc? overview document conventions acronyms used the following table lists the acronyms that are used in this doc- ument. units of measure a units of measure table is located in the electrical specifica- tions section. table 2-1 on page 9 lists all the abbreviations used to measure the psoc devices. numeric naming hexidecimal numbers are represented with all letters in upper- case with an appended lowercase ?h? (for example, ?14h? or ?3ah?). hexidecimal numbers may also be represented by a ?0x? prefix, the c coding convention. binary numbers have an appended lowercase ?b? (e.g., 01010100b? or ?01000011b?). numbers not indicated by an ?h?, ?b?, or 0x are decimal. table of contents for an in depth discussion and more information on your psoc device, obtain the psoc mixed-signal array technical refer- ence manual on http://www.cypress.com . this document encompasses and is organized into the following chapters and sections. 1. pin information ............................................................. 7 1.1 pinouts ................................................................... 7 1.1.1 24-pin part pinout ..................................... 7 1.1.2 32-pin part pinout ..................................... 8 2. electrical specifications .............................................. 9 2.1 absolute maximum ratings ................................. 10 2.2 operating temperature ........................................ 10 2.3 dc electrical characteristics ................................ 10 2.3.1 dc chip-level specifications ................... 10 2.3.2 dc general purpose io specifications .... 11 2.3.3 dc analog mux bus specifications .......... 12 2.3.4 dc por and lvd specifications ............. 12 2.3.5 dc programming specifications ............... 13 2.4 ac electrical characteristics ................................ 14 2.4.1 ac chip-level specifications ................... 14 2.4.2 ac general purpose io specifications .... 15 2.4.3 ac comparator amplifier specifications .. 16 2.4.4 ac analog mux bus specifications .......... 16 2.4.5 ac external clock specifications ............. 17 2.4.6 ac programming specifications ............... 18 2.4.7 ac spi specifications ............................... 19 2.4.8 ac i2c specifications ............................... 20 3. packaging information ............................................... 21 3.1 packaging dimensions ......................................... 21 3.2 thermal impedances .......................................... 22 3.3 solder reflow peak temperature ........................ 23 4. ordering information .................................................. 24 4.1 ordering code definitions .................................... 24 5. sales and service information .................................. 25 5.1 revision history ................................................... 25 5.2 copyrights and code protection .......................... 25 acronym description ac alternating current adc analog-to-digital converter api application programming interface cpu central processing unit ct continuous time dac digital-to-analog converter dc direct current eco external crystal oscillator fsr full scale range gpio general purpose io gui graphical user interface hbm human body model ice in-circuit emulator ilo internal low speed oscillator imo internal main oscillator io input/output ipor imprecise power on reset lsb least-significant bit lvd low voltage detect msb most-significant bit pc program counter pll phase-locked loop por power on reset ppor precision power on reset psoc? programmable system-on-chip? pwm pulse width modulator sc switched capacitor slimo slow imo sram static random access memory
january 17, 2006 document no. 001-05356 rev. *a 7 1. pin information this chapter describes, lists, and illustrates the cy8c20334 and cy8c20434 psoc device pins and pinout configurations. 1.1 pinouts the cy8c20x34 psoc device is available in a variety of packages which are listed and illustrated in the following tables. every port pin (labeled with a ?p?) is capable of digital io and connection to the common analog bus. however, vss, vdd, and xres are not capable of digital io. 1.1.1 24-pin part pinout table 1-1. 24-pin part pinout (qfn**) pin no. type name description cy8c20334 24-pin psoc device digital analog 1 io i p2[5] 2 io i p2[3] 3 io i p2[1] 4 ioh i p1[7] i2c scl, spi ss 5 ioh i p1[5] i2c sda, spi miso 6 ioh i p1[3] spi clk 7 ioh i p1[1] clk*, i2c scl, spi mosi 8 nc no connection 9 power vss ground connection 10 ioh i p1[0] data*, i2c sda 11 ioh i p1[2] 12 ioh i p1[4] optional external clock input (extclk) 13 ioh i p1[6] 14 input xres active high external reset with internal pull down 15 io i p2[0] 16 io i p0[0] 17 io i p0[2] 18 io i p0[4] 19 io i p0[6] analog bypass 20 power vdd supply voltage 21 io i p0[7] 22 io i p0[5] 23 io i p0[3] integrating input 24 io i p0[1] legend a = analog, i = input, o = output, oh = 5 ma high output drive. * these are the issp pins, which are not high z at por (power on reset). see the psoc mixed-signal array technical reference manual for details. ** the center pad on the qfn package should be connected to ground (vss) for best mechanical, thermal, and electrical performan ce. if not connected to ground, it should be electrically floated and not connected to any other signal. qfn (top view ) ai, p2[5] ai, i2c scl, spi ss, p1[7] ai, i2c sda, spi miso, p1[5] ai, spi clk, p1[3] 1 2 3 4 5 6 18 17 16 15 14 13 p0[2], ai p0[0], ai 24 23 22 21 20 19 p0[3], ai p0[5], ai p0[7], ai vdd p0[4], ai 7 8 9 10 11 12 spi mosi, p1[1] ai, data*, i2c sda, p1[0] ai, p1[2] ai, p2[3] ai, p2[1] nc p1[6], ai ai, extclk, p1[4] xres p2[0], ai p0[6], ai ai, clk*, i2c scl p0[1], ai vss
january 17, 2006 document no. 001-05356 rev. *a 8 cy8c20x34 preliminary data sheet 1. pin information 1.1.2 32-pin part pinout table 1-2. 32-pin part pinout (qfn**) pin no. type name description cy8c20434 32-pin psoc device digital analog 1 io i p0[1] 2 io i p2[7] 3 io i p2[5] 4 io i p2[3] 5 io i p2[1] 6 io i p3[3] 7 io i p3[1] 8 ioh i p1[7] i2c scl, spi ss 9 ioh i p1[5] i2c sda, spi miso 10 ioh i p1[3] spi clk 11 ioh i p1[1] clk*, i2c scl, spi mosi 12 power vss ground connection 13 ioh i p1[0] data*, i2c sda 14 ioh i p1[2] 15 ioh i p1[4] optional external clock input (extclk) 16 ioh i p1[6] 17 input xres active high external reset with internal pull down 18 io i p3[0] 19 io i p3[2] 20 io i p2[0] 21 io i p2[2] 22 io i p2[4] 23 io i p2[6] 24 io i p0[0] 25 io i p0[2] 26 io i p0[4] 27 io i p0[6] analog bypass 28 power vdd supply voltage 29 io i p0[7] 30 io i p0[5] 31 io i p0[3] integrating input 32 power vss ground connection legend a = analog, i = input, o = output, oh = 5 ma high output drive. * these are the issp pins, which are not high z at por (power on reset). see the psoc mixed-signal array technical reference manual for details. ** the center pad on the qfn package should be connected to ground (vss) for best mechanical, thermal, and electrical performan ce. if not connected to ground, it should be electrically floated and not connected to any other signal. ai, p0[1] ai, p2[7] ai, p2[5] ai, p2[3] ai, p2[1] ai, p3[3] qfn (top view) 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 vss p0[3], ai p0[7], ai vdd p0[6], ai p0[4], ai p0[2], ai ai, p3[1] spi ss, p1[7] p0[0], a i p2[6], a i p3[0], a i xres ai, i2c sda, spi miso, p1[5] ai, spi clk, p1[3] ai, clk*, i2c scl, spi mosi, p1[1] vss ai, data*, i2c sda, p1[0] ai, p1[2] ai, extclk, p1[4] ai, p1[6] p2[4], a i p2[2], a i p2[0], a i p3[2], a i p0[5], ai ai, i2c scl
january 17, 2006 document no. 001-05356 rev. *a 9 2. electrical specifications this chapter presents the dc and ac electrical specifications of the cy8c20334 and cy8c20434 psoc devices. for the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. specifications are valid for -20 o c t a 70 o c and t j 85 o c as specified, except where noted. refer to table 2-10 for the electrical specifications on the internal main oscillator (imo) using slimo mode. figure 2-1a. voltage versus cpu frequency figure 2-1b. imo frequency trim options the following table lists the units of measure that are used in this chapter. table 2-1: units of measure symbol unit of measure symbol unit of measure o c degree celsius w microwatts db decibels ma milli-ampere ff femto farad ms milli-second hz hertz mv milli-volts kb 1024 bytes na nanoampere kbit 1024 bits ns nanosecond khz kilohertz nv nanovolts k ? kilohm ? ohm mhz megahertz pa picoampere m ? megaohm pf picofarad a microampere pp peak-to-peak f microfarad ppm parts per million h microhenry ps picosecond s microsecond sps samples per second v microvolts sigma: one standard deviation vrms microvolts root-mean-square v volts 5.25 4.75 3.00 750 khz 12 mhz cpu frequency vdd voltage 5.25 4.75 3.00 750 khz 6 mhz 12 mhz imo frequency vdd voltage 3.60 3 mhz 2.40 slimo mode=1 2.40 3 mhz v a l i d o p e r a t i n g r e g i o n slimo mode=1 slim o mode=0 slimo mode=1 slimo mode=0 2.70 slimo mode=1 slimo mode=0
january 17, 2006 document no. 001-05356 rev. *a 10 cy8c20x34 preliminary data sheet 2. electrical specifications 2.1 absolute maximum ratings 2.2 operating temperature 2.3 dc electrical characteristics 2.3.1 dc chip-level specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -20 c t a 70 c, 3.0v to 3.6v and -20 c t a 70 c, or 2.4v to 3.0v and -20 c t a 70 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 2-2. absolute maximum ratings symbol description min typ max units notes t stg storage temperature -55 +25 +100 o c recommended storage temperature is +25 c +/- 25 c. extended duration storage tempera- tures above 65 o c will degrade reliability. t a ambient temperature with power applied -20 ? +70 o c vdd supply voltage on vdd relative to vss -0.5 ? +6.0 v v io dc input voltage vss - 0.5 ? vdd + 0.5 v v ioz dc voltage applied to tri-state vss - 0.5 ? vdd + 0.5 v i mio maximum current into any port pin -25 ? +50 ma esd electro static discharge voltage 2000 ? ? v human body model esd. lu latch-up current ? ? 200 ma table 2-3. operating temperature symbol description min typ max units notes t a ambient temperature -20 ? +70 o c t j junction temperature -20 ? +85 o c the temperature rise from ambient to junction is package specific. see ?thermal impedances? on page 22 . the user must limit the power con- sumption to comply with this requirement. table 2-4. dc chip-level specifications symbol description min typ max units notes vdd supply voltage 2.40 ? 5.25 v see table titled ?dc por and lvd specifica- tions? on page 12 . i dd12 supply current, imo = 12 mhz ? 1.5 2.5 ma conditions are vdd = 3.0v, t a = 25 o c, cpu = 12 mhz. i dd6 supply current, imo = 6 mhz ? 1 1.5 ma conditions are vdd = 3.0v, t a = 25 o c, cpu = 6 mhz. i sb standby current ? 2.6 4 a vdd = 3.0v, t a = 25 o c, cpu = 6 mhz, -20c < ta < 70c.
january 17, 2006 document no. 001-05356 rev. *a 11 cy8c20x34 preliminary data sheet 2. electrical specifications 2.3.2 dc general purpose io specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -20 c t a 70 c, 3.0v to 3.6v and -20 c t a 70 c, or 2.4v to 3.0v and -20 c t a 70 c, respectively. typical parameters apply to 5v, 3.3v, and 2.7v at 25 c and are for design guidance only. table 2-5. 5v and 3.3v dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? v oh1 high output voltage port 0, 2, or 3 pins vdd - 0.2 ? ? v ioh < 10 a, vdd > 3.0v, maximum of 10 ma source current in all ios. v oh2 high output voltage port 0, 2, or 3 pins vdd - 0.9 ? ? v ioh = 1 ma, vdd > 3.0v, maximum of 20 ma source current in all ios. v oh3 high output voltage port 1 pins with ldo regulator disabled vdd - 0.2 ? ? v ioh < 10 a, vdd > 3.0v, maximum of 10 ma source current in all ios. v oh4 high output voltage port 1 pins with ldo regulator disabled vdd - 0.9 ? ? v ioh = 5 ma, vdd > 3.0v, maximum of 20 ma source current in all ios. v oh5 high output voltage port 1 pins with ldo regulator enabled 2.85 3.0 3.15 v ioh < 10 a, vdd > 3.1v, maximum of 4 ios all sourcing 5 ma. v oh6 high output voltage port 1 pins with ldo regulator enabled 2.2 ? ? v ioh = 5 ma, vdd > 3.1v, maximum of 20 ma source current in all ios. v ol low output voltage ? ? 0.75 v iol = 20 ma, vdd > 3v, maximum of 60 ma sink current on even port pins (for example, p0[2] and p1[4]) and 60 ma sink current on odd port pins (for example, p0[3] and p1[5]). v il input low voltage ? ? 0.8 v vdd = 3.0 to 5.25. v ih input high voltage 2.0 ? v vdd = 3.0 to 5.25. v h input hysteresis voltage ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input 0.5 1.7 5 pf package and pin dependent. temp = 25 o c. c out capacitive load on pins as output 0.5 1.7 5 pf package and pin dependent. temp = 25 o c. table 2-6. 2.7v dc gpio specifications symbol description min typ max units notes r pu pull-up resistor 4 5.6 8 k ? v oh1 high output voltage port 0, 2, or 3 pins vdd - 0.2 ? ? v ioh < 10 a, maximum of 10 ma source current in all ios. v oh2 high output voltage port 0, 2, or 3 pins vdd - 0.5 ? ? v ioh = 0.2 ma, maximum of 10 ma source cur- rent in all ios. v oh3 high output voltage port 1 pins with ldo regulator disabled vdd - 0.2 ? ? v ioh < 10 a, maximum of 10 ma source current in all ios. v oh4 high output voltage port 1 pins with ldo regulator disabled vdd - 0.5 ? ? v ioh = 2 ma, maximum of 10 ma source current in all ios. v ol low output voltage ? ? 0.75 v iol = 10 ma, maximum of 30 ma sink current on even port pins (for example, p0[2] and p1[4]) and 30 ma sink current on odd port pins (for example, p0[3] and p1[5]). v il input low voltage ? ? 0.8 v vdd = 2.4 to 3.0v. v ih input high voltage 2.0 ? v vdd = 2.4 to 3.0v. v h input hysteresis voltage ? 60 ? mv i il input leakage (absolute value) ? 1 ? na gross tested to 1 a. c in capacitive load on pins as input 0.5 1.7 5 pf package and pin dependent. temp = 25 o c. c out capacitive load on pins as output 0.5 1.7 5 pf package and pin dependent. temp = 25 o c.
january 17, 2006 document no. 001-05356 rev. *a 12 cy8c20x34 preliminary data sheet 2. electrical specifications 2.3.3 dc analog mux bus specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -20 c t a 70 c, 3.0v to 3.6v and -20 c t a 70 c, or 2.4v to 3.0v and -20 c t a 70 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. 2.3.4 dc por and lvd specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -20 c t a 70 c, 3.0v to 3.6v and -20 c t a 70 c, or 2.4v to 3.0v and -20 c t a 70 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 2-7. dc analog mux bus specifications symbol description min typ max units notes r sw switch resistance to common analog bus ? ? 400 800 ? ? vdd 2.7v 2.4v vdd 2.7v r vdd resistance of initialization switch to vdd ? ? 800 ? table 2-8. dc por and lvd specifications symbol description min typ max units notes v ppor0 v ppor1 v ppor2 vdd value for ppor trip porlev[1:0] = 00b porlev[1:0] = 01b porlev[1:0] = 10b ? 2.36 2.60 2.82 2.40 2.65 2.95 v v v vdd must be greater than or equal to 2.5v during startup, reset from the xres pin, or reset from watchdog. v lv d0 v lv d1 v lv d2 v lv d3 v lv d4 v lv d5 v lv d6 v lv d7 vdd value for lvd trip vm[2:0] = 000b vm[2:0] = 001b vm[2:0] = 010b vm[2:0] = 011b vm[2:0] = 100b vm[2:0] = 101b vm[2:0] = 110b vm[2:0] = 111b 2.40 2.64 2.85 2.95 3.06 ? ? 4.62 2.45 2.71 2.92 3.02 3.13 ? ? 4.73 2.51 a 2.78 b 2.99 c 3.09 3.20 ? ? 4.83 a. always greater than 50 mv above v ppor (porlev = 00) for falling supply. b. always greater than 50 mv above v ppor (porlev = 01) for falling supply. c. always greater than 50 mv above v ppor (porlev = 10) for falling supply. v v v v v v v v
january 17, 2006 document no. 001-05356 rev. *a 13 cy8c20x34 preliminary data sheet 2. electrical specifications 2.3.5 dc programming specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -20 c t a 70 c, 3.0v to 3.6v and -20 c t a 70 c, or 2.4v to 3.0v and -20 c t a 70 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 2-9. dc programming specifications symbol description min typ max units notes vdd iwrite supply voltage for flash write operations 2.70 ? ? v i ddp supply current during programming or verify ? 5 25 ma v ilp input low voltage during programming or verify ? ? 0.8 v v ihp input high voltage during programming or verify 2.2 ? ? v i ilp input current when applying vilp to p1[0] or p1[1] during programming or verify ? ? 0.2 ma driving internal pull-down resistor. i ihp input current when applying vihp to p1[0] or p1[1] during programming or verify ? ? 1.5 ma driving internal pull-down resistor. v olv output low voltage during programming or verify ? ? vss + 0.75 v v ohv output high voltage during programming or verify vdd - 1.0 ? vdd v flash enpb flash endurance (per block) 50,000 ? ? ? erase/write cycles per block. flash ent flash endurance (total) a a. a maximum of 36 x 50,000 block endurance cycles is allowed. this may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). 1,800,000 ? ? ? erase/write cycles. flash dr flash data retention 10 ? ? ye ars
january 17, 2006 document no. 001-05356 rev. *a 14 cy8c20x34 preliminary data sheet 2. electrical specifications 2.4 ac electrical characteristics 2.4.1 ac chip-level specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -20 c t a 70 c, 3.0v to 3.6v and -20 c t a 70 c, or 2.4v to 3.0v and -20 c t a 70 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 2-10. 3.3v ac chip-level specifications symbol description min typ max units notes f cpu1 cpu frequency (3.3v nominal) 0.75 ? 12.6 mhz 12 mhz only for slimo mode = 0. f 32k1 internal low speed oscillator frequency 15 32 64 khz f imo12 internal main oscillator stability for 12 mhz (commercial temperature) a a. 0 to 70 c ambient, vdd = 3.3 v. 11.4 12 12.6 mhz trimmed for 3.3v operation using factory trim values. see figure 2-1b, slimo mode = 0. f imo6 internal main oscillator stability for 6 mhz (commercial temperature) 5.70 6.0 6.30 mhz trimmed for 3.3v operation using factory trim values. see figure 2-1b, slimo mode = 1. dc imo duty cycle of imo 40 50 60 % t ramp supply ramp time 0 ? ? s table 2-11. 2.7v ac chip-level specifications symbol description min typ max units notes f cpu1 cpu frequency (2.7v nominal) 0.75 ? 3.25 mhz f 32k1 internal low speed oscillator frequency 8 32 96 khz f imo12 internal main oscillator stability for 12 mhz (commercial temperature) a a. 0 to 70 c ambient, vdd = 3.3 v. 11.0 12 12.9 mhz trimmed for 2.7v operation using factory trim values. see figure 2-1b, slimo mode = 0. f imo6 internal main oscillator stability for 6 mhz (commercial temperature) 5.60 6.0 6.40 mhz trimmed for 2.7v operation using factory trim values. see figure 2-1b, slimo mode = 1. dc imo duty cycle of imo 40 50 60 % t ramp supply ramp time 0 ? ? s
january 17, 2006 document no. 001-05356 rev. *a 15 cy8c20x34 preliminary data sheet 2. electrical specifications 2.4.2 ac general purpose io specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -20 c t a 70 c, 3.0v to 3.6v and -20 c t a 70 c, or 2.4v to 3.0v and -20 c t a 70 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. figure 2-2. gpio timing diagram table 2-12. 5v and 3.3v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 6 mhz normal strong mode, port 1. trise023 rise time, strong mode ports 0, 2, 3 15 ? 80 ns vdd = 3.0 to 3.6v, 10% - 90% trise1 rise time, strong mode port 1 10 ? 50 ns vdd = 3.0 to 3.6v, 10% - 90% tfall fall time, strong mode all ports 10 ? 50 ns vdd = 3.0 to 3.6v, 10% - 90% table 2-13. 2.7v ac gpio specifications symbol description min typ max units notes f gpio gpio operating frequency 0 ? 1.5 mhz normal strong mode, port 1. trise023 rise time, strong mode ports 0, 2, 3 15 ? 100 ns vdd = 2.4 to 3.0v, 10% - 90% trise1 rise time, strong mode port 1 10 ? 70 ns vdd = 2.4 to 3.0v, 10% - 90% tfall fall time, strong mode all ports 10 ? 70 ns vdd = 2.4 to 3.0v, 10% - 90% tfall trise023 trise1 90% 10% gpio pin output v oltage
january 17, 2006 document no. 001-05356 rev. *a 16 cy8c20x34 preliminary data sheet 2. electrical specifications 2.4.3 ac comparator amplifier specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -20 c t a 70 c, 3.0v to 3.6v and -20 c t a 70 c, or 2.4v to 3.0v and -20 c t a 70 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. 2.4.4 ac analog mux bus specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -20 c t a 70 c, 3.0v to 3.6v and -20 c t a 70 c, or 2.4v to 3.0v and -20 c t a 70 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 2-14. ac operational amplifier specifications symbol description min typ max units notes t comp comparator response time, 50 mv overdrive 100 200 ns ns vdd 3.0v. 2.4v < vcc < 3.0v. table 2-15. ac analog mux bus specifications symbol description min typ max units notes f sw switch rate ? ? 3.17 mhz
january 17, 2006 document no. 001-05356 rev. *a 17 cy8c20x34 preliminary data sheet 2. electrical specifications 2.4.5 ac external clock specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -20 c t a 70 c, 3.0v to 3.6v and -20 c t a 70 c, or 2.4v to 3.0v and -20 c t a 70 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 2-16. 5v ac external clock specifications symbol description min typ max units notes f oscext frequency 0.750 ?12.6mhz ? high period 20.6 ? 5300 ns ? low period 20.6 ? ?ns ? power up imo to switch 150 ? ? s table 2-17. 3.3v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.750 ? 12.6 mhz maximum cpu frequency is 12 mhz at 3.3v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. ? high period with cpu clock divide by 1 41.7 ? 5300 ns ? low period with cpu clock divide by 1 41.7 ? ?ns ? power up imo to switch 150 ? ? s table 2-18. 2.7v ac external clock specifications symbol description min typ max units notes f oscext frequency with cpu clock divide by 1 0.750 ? 3.08 0 mhz maximum cpu frequency is 3 mhz at 2.7v. with the cpu clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. f oscext frequency with cpu clock divide by 2 or greater 0.15 ? 6.35 mhz if the frequency of the external clock is greater than 3 mhz, the cpu clock divider must be set to 2 or greater. in this case, the cpu clock divider will ensure that the fifty percent duty cycle requirement is met. ? high period with cpu clock divide by 1 160 ? 5300 ns ? low period with cpu clock divide by 1 160 ? ?ns ? power up imo to switch 150 ? ? s
january 17, 2006 document no. 001-05356 rev. *a 18 cy8c20x34 preliminary data sheet 2. electrical specifications 2.4.6 ac programming specifications the following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -20 c t a 70 c, 3.0v to 3.6v and -20 c t a 70 c, or 2.4v to 3.0v and -20 c t a 70 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 2-19. ac programming specifications symbol description min typ max units notes t rsclk rise time of sclk 1 ? 20 ns t fsclk fall time of sclk 1 ? 20 ns t ssclk data set up time to falling edge of sclk 40 ? ? ns t hsclk data hold time from falling edge of sclk 40 ? ? ns f sclk frequency of sclk 0 ? 8 mhz t eraseb flash erase time (block) ? 15 ? ms t write flash block write time ? 30 ? ms t dsclk data out delay from falling edge of sclk ? ? 45 ns 3.6 < vdd t dsclk3 data out delay from falling edge of sclk ? ? 50 ns 3.0 vdd 3.6 t dsclk2 data out delay from falling edge of sclk ? ? 70 ns 2.4 vdd 3.0
january 17, 2006 document no. 001-05356 rev. *a 19 cy8c20x34 preliminary data sheet 2. electrical specifications 2.4.7 ac spi specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -20 c t a 70 c, 3.0v to 3.6v and -20 c t a 70 c, or 2.4v to 3.0v and -20 c t a 70 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. table 2-20. 5v and 3.3v ac spi specifications symbol description min typ max units notes f spim maximum input clock frequency selection, master ? ? 6.3 mhz output clock frequency is half of input clock rate. f spis maximum input clock frequency selection, slave ? ? 2.05 mhz t ss width of ss_ negated between transmissions 50 ? ? ns table 2-21. 2.7v ac spi specifications symbol description min typ max units notes f spim maximum input clock frequency selection, master ? ? 3.15 mhz output clock frequency is half of input clock rate. f spis maximum input clock frequency selection, slave ? ? 1.025 mhz t ss width of ss_ negated between transmissions 50 ? ? ns
january 17, 2006 document no. 001-05356 rev. *a 20 cy8c20x34 preliminary data sheet 2. electrical specifications 2.4.8 ac i 2 c specifications the following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75v to 5.25v and -20 c t a 70 c, 3.0v to 3.6v and -20 c t a 70 c, or 2.4v to 3.0v and -20 c t a 70 c, respectively. typical parameters apply to 5v, 3.3v, or 2.7v at 25 c and are for design guidance only. figure 2-3. definition for timing for fast/standard mode on the i 2 c bus table 2-22. ac characteristics of the i 2 c sda and scl pins for vdd 3.0v symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 0 400 khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ?0.6 ? s t lowi2c low period of the scl clock 4.7 ?1.3 ? s t highi2c high period of the scl clock 4.0 ?0.6 ? s t sustai2c set-up time for a repeated start condition 4.7 ?0.6 ? s t hddati2c data hold time 0 ?0 ? s t sudati2c data set-up time 250 ? 100 a a. a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su;dat 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such device does stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su;dat = 1000 + 250 = 1250 ns (according to the standard-mode i2c-bus specification) before the scl line is released. ?ns t sustoi2c set-up time for stop condition 4.0 ?0.6 ? s t bufi2c bus free time between a stop and start condition 4.7 ?1.3 ? s t spi2c pulse width of spikes are suppressed by the input fil- ter. ? ? 0 50 ns table 2-23. 2.7v ac characteristics of the i 2 c sda and scl pins (fast mode not supported) symbol description standard mode fast mode units notes min max min max f scli2c scl clock frequency 0 100 ? ? khz t hdstai2c hold time (repeated) start condition. after this period, the first clock pulse is generated. 4.0 ? ? ? s t lowi2c low period of the scl clock 4.7 ? ? ? s t highi2c high period of the scl clock 4.0 ? ? ? s t sustai2c set-up time for a repeated start condition 4.7 ? ? ? s t hddati2c data hold time 0 ? ? ? s t sudati2c data set-up time 250 ? ? ?ns t sustoi2c set-up time for stop condition 4.0 ? ? ? s t bufi2c bus free time between a stop and start condition 4.7 ?? ? s t spi2c pulse width of spikes are suppressed by the input fil- ter. ? ???ns sda scl s sr s p t bufi2c t spi2c t hdstai2c t sustoi2c t sustai2c t lowi2c t highi2c t hddati2c t hdstai2c t sudati2c
january 17, 2006 document no. 001-05356 rev. *a 21 3. packaging information this chapter illustrates the packaging specifications for the cy8c20x34 psoc device, along with the thermal impedances for each package. important note emulation tools may require a larger area on the target pcb than the chip?s footprint. for a detailed description of the emulation tools? dimensions, refer to the document titled psoc emulator pod dimensions at http://www.cypress.com/support/link.cfm?mr=poddim . 3.1 packaging dimensions figure 3-1. 24-lead (4x4 mm) qfn 51-85203 **
january 17, 2006 document no. 001-05356 rev. *a 22 cy8c20x34 preliminary data sheet 3. packaging information figure 3-2. 32-lead (5x5 mm) qfn important note for information on the preferred dimensions for mounting qfn packages, see the following application note at http://www.amkor.com/products/notes_papers/mlfappnote.pdf . 3.2 thermal impedances table 3-1. thermal impedances per package package typical ja * typical jc 24 qfn** 117 o c/w 41 o c/w 32 qfn** 14.5 o c/w 39 o c/w * t j = t a + power x ja ** to achieve the thermal impedance specified for the ** package, the center thermal pad should be soldered to the pcb ground plane. e-pad x, y for this product is 3.53 mm, 3.53 mm ( +/- 0.11 mm) 001-063351 **
january 17, 2006 document no. 001-05356 rev. *a 23 cy8c20x34 preliminary data sheet 3. packaging information 3.3 solder reflow peak temperature following is the minimum solder reflow peak temperature to achieve good solderability. table 3-2. solder reflow peak temperature package minimum peak temperature* maximum peak temperature 24 qfn 240 o c 260 o c 32 qfn 240 o c 260 o c *higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220+/-5 o c with sn-pb or 245+/-5 o c with sn-ag-cu paste. refer to the solder manufacturer specifications.
january 17, 2006 document no. 001-05356 rev. *a 24 4. ordering information the following table lists the cy8c20334 and cy8c20434 psoc device?s key package features and ordering codes. 4.1 ordering code definitions table 4-1. psoc device key features and ordering information package ordering code flash (bytes) sram (bytes) digital blocks capsense blocks digital io pins analog inputs a analog outputs xres pin 24 pin (4x4 mm) qfn CY8C20334-12LFXC 8k 512 0 1 20 20 a a. dual-function digital io pins also connect to the common analog mux. 0 yes 24 pin (4x4 mm) qfn (tape and reel) CY8C20334-12LFXCt 8k 512 0 1 20 20 a 0 yes 32 pin (5x5 x 0.6 mm) qfn cy8c20434-12lkc 8k 512 0 1 28 28 a 0 yes 32 pin (5x5 x 0.6 mm) qfn (tape and reel) cy8c20434-12lkct 8k 512 0 1 28 28 a 0 yes c y 8 c 20 xxx-12xx package type: thermal rating: px = pdip pb-free c = commercial sx = soic pb-free i = industrial pvx = ssop pb-free e = extended lfx = qfn pb-free lkc = qfn pb-free ax = tqfp pb-free speed: 12 mhz part number family code technology code: c = cmos marketing code: 8 = cypress microsystems company id: cy = cypress
january 17, 2006 ? cypress semiconductor corp. 2005-2006 ? document no. 001-05356 rev. *a 25 5. sales and service information to obtain information about cypress semiconductor or psoc sales and technical support, reference the following information. cypress semiconductor 5.1 revision history 5.2 copyrights and code protection copyrights ? cypress semiconductor corp. 2005-2006. all rights reserved. psoc designer?, programmable system-on-chip?, and psoc express ar e trademarks and psoc? is a registered trademark of cypress semiconductor corp. all other trademarks or registered trademarks referenced herein are prope rty of the respective corporations. the information contained herein is subject to change without notice. cypress semiconductor assumes no responsibility for the u se of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license under patent or other rights. cypress semi conductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in s ignificant injury to the user. the inclusion of cypress semiconductor products in life-support systems applicatio n implies that the manufacturer assumes all risk of such use a nd in doing so indemnifies cypress semiconductor against all charges. cypress semiconductor products are not warranted nor intended to be used for medical, life-s upport, life-saving, critical control or safety applications, unless pursuant to an express written agreement with cypress semiconductor. flash code protection note the following details of the flash code protection features on cypress semiconductor psoc devices. cypress semiconductor products meet the specifications contained in their particular data sheets. cypress semiconductor believe s that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. there may be methods, unknown to cypress semiconductor, that can breach the code protection features. any of these methods, to our knowledge, would be dishonest and possibly illegal. neither cypress semi conductor nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as "u nbreakable." cypress semiconductor is willing to work with the customer who is concerned about the integrity of their code. code protection is constantly evolving. we at cypress semiconductor are committed to continuously improving the code protection features of our products. 198 champion court san jose, ca 95134 408.943.2600 web links: company information ? http://www.cypress.com sales ? http://www.cypress.com/aboutus/sales_locations.cfm technical support ? http://www.cypress.com/support/login.cfm document title : capsense cy8c20334 and cy8c20434 preliminary data sheet document number : 001-05356 revision ecn # issue date origin of change description of change ** 404571 see ecn hmt new silicon and document (revision **). *a 418513 see ecn hmt update electrical specs., including storage temperature and maximum input clock frequency. update features and analog system overview. modify 32-pin qfn e-pad dimensions. add new 32-pin qfn. add high output drive indicator to all p1[x] pinouts. update trademarks. distribution : external/public posting : none

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